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HC- CP4-27B4-10D, 100 Gb/s CFP4 LR4 Transceiver

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Product Features  

Compliant with 100GBASE-LR4

Support line rates from 103.125 Gbps to 111.81 Gbps

Integrated LAN WDM TOSA / ROSA for up to 10 km reach over SMF

Digital Diagnostics Monitoring Interface

Duplex LC optical receptacle

No external reference clock

Single 3.3 V power supply

Case operating temperature range:0°C to 70°C  

Power dissipation < 6W

 

Application

Local Area Network (LAN)

Data Center

Ethernet switches and router applications


General Description

    100G CFP4 LR4 optical Transceiver integrates receiver and transmitter path on one module. In the transmit side, four lanes of serial data streams are recovered, retimed, and passed to four laser drivers. The laser drivers control four EMLs (Electric-absorption Modulated Lasers) with center wavelength of 1296 nm, 1300nm, 1305nm and 1309 nm. The optical signals are multiplexed to a single –mode fiber through an industry standard LC connector. In the receive side, the four lanes of optical data streams are optically de-multiplexed by the integrated optical de-multiplexer. Each data stream is recovered by a PIN photo-detector and trans-impedance amplifier, retimed. This module features a hot-pluggable electrical interface, low power consumption and MDIO management interface.

     The module provides an aggregated signaling rate from 103.125 Gbps to 111.81 Gbps. It is compliant with IEEE 802.3 ba 100GBASE-LR4 and ITU-T G.959.1, and OIF CEI-28G-VSR. The MDIO management interface complies with IEEE 802.3 Clause 45 standard. The transceiver complies with CFP MSA CFP4 Hardware Specification, CFP MSA Management Interface Specification, and OIF CEI-28G-VSR standards. A block diagram is shown in Figure 1. 


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Figure 1. CFP4 LR4 Optical Transceiver functional block diagram



Transmitter

The transmitter path converts four lanes of serial NRZ electrical data from line rate of 25.78 Gbps to 27.95 Gbps to a standard compliant optical signal. Each signal path accepts a 100 Ω differential 100 mV peak-to-peak to 900 mV peak-to-peak 25 Gbps electrical signal on TDxn and TDxp pins. Inside the module, each differential pair of electric signals is input to a CDR (clock-data recovery) chip. The recovered and retimed signals are then passed to a laser driver which transforms the small swing voltage to an output modulation that drives a EML laser. The laser drivers control four EMLs with center wavelengths of 1295.56 nm, 1300.05 nm, 1304.58 nm and 1309.14 nm. The optical signals from the four lasers are multiplexed together optically. The combined optical signals are coupled to single-mode optical fiber through an industry standard LC optical connector.

Receiver

The receiver takes incoming combined four lanes optical data from line rate of 25.78 Gbps to 27.95 Gbps through an industry standard LC optical connector. The four incoming wavelengths are separated by an optical de-multiplexer into four separated channels. Each output is coupled to a PIN photo-detector. The electrical currents from each PIN photo-detector are converted to a voltage with a high-gain trans-impedance amplifier. The electrical output is recovered and retimed by the CDR chip. The four lanes of reshaped electrical signals are output to RDxp and RDxn pins.

Low Speed Signaling

Low speed signaling is based on low voltage CMOS (LVCMOS) operating at a nominal voltage of 3.3 V for the control and alarm signals, and at a nominal voltage of 1.2 V for MDIO address, clock and data signals. All low speed inputs and outputs are based on the CFP MSA CFP4 Hardware Specification and CFP MSA Management Interface Specification.

MDC/MDIO: Management interface clock and data lines.

PRTADR0, 1, 2: Input pins. MDIO physical port addresses.

GLB_ALEMn: Output pin. When asserted low indicates that the module has detected an alarm condition in any MDIO alarm register.

TX_Disable: Input pin. When asserted high or left open the transmitter output is turned off. When Tx_Dsiable is asserted low or grounded the module transmitter is operating normally. Pulled up with 4.7 kΩ to 10 kΩ resistors to 3.3 V inside the CFP4 module.

MOD_LOPWR: Input pin. When asserted high or left open the CFP4 module is in low power mode. When asserted low or grounded the module is operating normally. Pulled up with 4.7 kΩ to 10 kΩ resistors to 3.3 V inside the CFP4 module.

MOD_RSTn: Input pin. When asserted low or grounded the module is in Reset mode. When asserted high or left open the CFP4 module is operating normally after an initialization process. Pulled down with 4.7 kΩ to 10 kΩ resistors to ground inside the CFP4 module.

Mod_ABS: Output pin. Asserted high when the CFP4 module is absent and is pulled low when the CFP4 module is inserted.

RX_LOS: Output pin. Asserted high when insufficient optical power for reliable signal reception is received.



      Absolute Maximum Ratings

Parameter

Symbol

Min.

Typ.

Max.

Unit

Note

Storage Temperature

Ts

-40

-

85

ºC


Relative Humidity

RH

5

-

95

%


Power Supply Voltage

VCC

-0.3

-

4

V


Signal Input Voltage


Vcc-0.3

-

Vcc+0.3

V


Receive Input Optical Power (Damage

threshold)

Pdmg



5.0

dBm




      Low Speed Electrical Characteristics

Parameter

Symbol

Min

Typ.

Max

Unit

Notes

Supply currents and voltages

Voltage

Vcc

3.2

3.3

3.4

V

With Respect to

GND

Supply current

Icc



1.8

A


Power dissipation

Pwr



6.0

W


Power dissipation (low power

mode)

Plp



1.0

W


Low speed control and sense signals, 3.3 V   LVCMOS

Outputs low voltage

Vol

-0.3


0.2

V

IOH=100 μA

Output high voltage

Voh

Vcc-0.2


Vcc+0.3

V

IOH=-100 μA

Input low voltage

Vil

-0.3


0.8

V


Input high voltage

Vih

2


Vcc3+ 0.3

V


Input leakage current

Iin

-10


10

μA


Low speed control and sense signals, 1.2 V LVCMOS

Outputs low voltage

Vol

-0.3


0.2

V


Output high voltage

Voh

1.0


1.5

V


Output low current

Iol

4



mA


Output high current

Ioh



-4

mA


Input low voltage

Vil

-0.3


0.36

V


Input high voltage

Vih

0.84


1.5

V


Input leakage current

Iin

-100


100

μA


Input capacitance

C



10

pF


MDC clock rate


0.1


4

MHz



      High Speed Electrical Specifications 


Parameter

Symbol

Min

Max

Unit

Notes

Transmitter electrical input from host

Differential voltage pk-pk



900

mV


Common mode noise (rms)



17.5

mV


Differential termination mismatch



10

%


Transition time


10


ps

20/80%

Common mode voltage


-0.3

2.8

V


Receiver electrical output to host

Differential voltage pk-pk



900

mV


Common mode noise (rms)



17.5

mV


Differential termination mismatch



10

%


Transition time


9.5


ps

20/80%



       MDIO Management Interface 

   The HC CFP4 Optical Transceiver incorporates MDIO management interface which is used for serial ID, digital diagnostics, and certain control and status report functions. The CFP4 transceiver supports MDIO pages 8000h NVR 1 Based ID registers, 8080h NVR 2 Extended ID registers, 8100h NVR 3 network lane specific registers , 8180h NVR 4 registers ,and pages A000h module VR 1 registers(module level control and DDM registers), A200h network lane VR 1 registersA280h network lane VR 2 registers,A400h host lane VR1 specific registers.

   Details of the protocol and interface are explicitly described in CFP MSA Management Interface Specification. Please refer to the specifications for design reference.


       Optical Transmitter Characteristics


Parameter

Symbol

Min

Typ.

Max

Unit

Notes

Signaling rate, each   lane



25.78125


Gbps


 

 

 

 

Lane wavelengthrange


1294.53

1295.56

1296.5

9

nm



1299.02

1300.05

1301.0

9

nm



1303.54

1304.58

1305.6

3

nm



1308.09

1309.14

1310.1

9

nm


Rate tolerance


-100


100

ppm

From normal rate

Side-mode suppression ratio

SMSR

30



dB


Total launch power




10.5

dBm


Average launch power, each

lane

Pavg

-4.3


4.5

dBm


Extinction Ratio

ER

4



dB


Optical modulation   amplitude,

each lane (OMA)

 

OMA

 

-1.3


 

4.5

 

dBm


Difference in launch power between any two lanes

(OMA)




 

5

 

dB


Transmitter and Dispersion

Penalty, each lane

TDP



2.2

dB


Average launch power of OFF

transmitter, each lane




 

-30

 

dBm


Relative Intensity Noise

RIN20O

MA



-130

dB/Hz


Transmitter reflectance




-12

dB


Transmitter eye mask {X1, X2,

X3, Y1, Y2, Y3}


 

{0.25, 0.4, 0.45, 0.25, 0.28, 0.4}





        Optical Receiver Characteristics

Parameter

Symbol

Min

Typ.

Max

Unit

Notes

Signaling rate, each   lane



25.78125


Gbps


 

Rate tolerance


 

-100


 

100

 

ppm

From normal

rate

Average receive power,

each lane

Pavg

-10.6


4.5

dBm


Receive max power, each

lane (OMA)




4.5

dBm


Difference in launch power

between any two lanes

(OMA)




 

5.5

 

dB


Receiver Sensitivity (OMA),

each lane

 

Rsen



 

-8.6

 

dBm

 

1

Stressed Receiver Sensitivity

(OMA), each lane

 

SRS



 

-6.8

 

dBm


Stressed receiver sensitivity test conditions

Vertical eye closure

penalty, each lane

VECP


1.8


dB


Stressed sys J2 jitter,

each lane

J2


0.3


UI

2

Stressed sys J9 jitter,

each lane

J9


0.47


UI

2

Receiver reflectance




-26

dB


LOS Assert

LOSA

-30



dBm


LOS De-assert

LOSD



-12

dBm


LOS Hysteresis


0.5


4

dB


1.     Receiver sensitivity (OMA), each lane, is informative.

2.     Vertical eye closure penalty, stressed eye J2 Jitter, and stressed   eye J9 Jitter are test conditions for measuring stressed receiver   sensitivity. They are not characteristics of the receiver.



Lower Memory Map

The lower 128 bytes of the 2-wire serial bus address space, see Table 1, is used to access a variety of

measurements and diagnostic functions, a set of control functions, and a means to select which of the various upper memory map pages are accessed on subsequent reads. This portion of the address space is always directly addressable and thus is chosen for monitoring and control functions that may need to be repeatedly accessed. The definition of identifier field is the same as page 00h Byte 128.


Table 1— Lower Memory Map

Byte Address

Description

Type

0

Identifier (1 Byte)

Read-Only

1-2

Status (2 Bytes)

Read-Only

3-21

Interrupt Flags (19 Bytes)

Read-Only

22-33

Module Monitors (12 Bytes)

Read-Only

34-81

Channel Monitors (48 Bytes)

Read-Only

82-85

Reserved (4 Bytes)

Read-Only

86-97

Control (12 Bytes)

Read/Write

98-99

Reserved (2 Bytes)

Read/Write

100-106

Module and Channel Masks (7 Bytes)

Read/Write

107-118

Reserved (12 Bytes)

Read/Write

119-122

Password Change Entry Area (optional) (4 Bytes)

Read/Write

123-126

Password Entry Area (optional) (4 Bytes)

Read/Write

127

Page Select Byte

Read/Write




      Outline Dimension:mm


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